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ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
16 years 4 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert
DATE
2009
IEEE
127views Hardware» more  DATE 2009»
16 years 1 months ago
Process variation aware thread mapping for Chip Multiprocessors
Abstract—With the increasing scaling of manufacturing technology, process variation is a phenomenon that has become more prevalent. As a result, in the context of Chip Multiproce...
Shengyan Hong, Sri Hari Krishna Narayanan, Mahmut ...
MUE
2009
IEEE
252views Multimedia» more  MUE 2009»
16 years 1 months ago
DDoS Detection and Traceback with Decision Tree and Grey Relational Analysis
As modern life becomes increasingly closely bound to the Internet, network security becomes increasingly important. Like it or not, we all live under the shadow of network threats...
Yi-Chi Wu, Huei-Ru Tseng, Wuu Yang, Rong-Hong Jan
ICPP
2009
IEEE
16 years 1 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...
ICPP
2009
IEEE
16 years 1 months ago
Improving Resource Availability by Relaxing Network Allocation Constraints on Blue Gene/P
— High-end computing (HEC) systems have passed the petaflop barrier and continue to move toward the next frontier of exascale computing. As companies and research institutes con...
Narayan Desai, Darius Buntinas, Daniel Buettner, P...