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DFT
1999
IEEE
75views VLSI» more  DFT 1999»
15 years 11 months ago
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths
Fault identification capabilities are becoming increasingly important in modern designs, not only in support of design debugging methodologies, but also for the purpose of process...
Yiorgos Makris, Alex Orailoglu
EUROMICRO
1999
IEEE
15 years 11 months ago
Software Synthesis for System Level Design Using Process Execution Trees
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
Leo J. van Bokhoven, Jeroen Voeten, Marc Geilen
HPCA
1999
IEEE
15 years 11 months ago
The Synergy of Multithreading and Access/Execute Decoupling
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
Joan-Manuel Parcerisa, Antonio González
CONCUR
1993
Springer
15 years 11 months ago
Loop Parallelization in the Polytope Model
During the course of the last decade, a mathematical model for the parallelization of FOR-loops has become increasingly popular. In this model, a (perfect) nest of r FOR-loops is r...
Christian Lengauer
SIGMETRICS
1993
ACM
118views Hardware» more  SIGMETRICS 1993»
15 years 11 months ago
An Analytic Performance Model of Disk Arrays
As disk arrays become widely used, tools for understanding and analyzing their performance become increasingly important. In particular, performance models can be invaluable in bo...
Edward K. Lee, Randy H. Katz