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IPPS
2002
IEEE
15 years 11 months ago
Hierarchical Interconnects for On-Chip Clustering
In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of cl...
Aneesh Aggarwal, Manoj Franklin
ISCA
2002
IEEE
102views Hardware» more  ISCA 2002»
15 years 11 months ago
Implementing Optimizations at Decode Time
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
Ilhyun Kim, Mikko H. Lipasti
207
Voted
ISSS
2002
IEEE
154views Hardware» more  ISSS 2002»
15 years 11 months ago
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edw...
IWPC
2002
IEEE
15 years 11 months ago
Dependence-Cache Slicing: A Program Slicing Method Using Lightweight Dynamic Information
When we try to debug or to comprehend a large program, it is important to separate suspicious program portions from the overall source program. Program slicing is a promising tech...
Tomonori Takada, Fumiaki Ohata, Katsuro Inoue
LCN
2002
IEEE
15 years 11 months ago
A Comparative Throughput Analysis of Scalable Coherent Interface and Myrinet
It has become increasingly popular to construct large parallel computers by connecting many inexpensive nodes built with commercial-off-the-shelf (COTS) parts. These clusters can ...
Sarp Millich, Alan D. George, Sarp Oral