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ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
16 years 3 months ago
A linear-time approach for static timing analysis covering all process corners
Abstract—Manufacturing process variations lead to circuit timing variability and a corresponding timing yield loss. Traditional corner analysis consists of checking all process c...
Sari Onaissi, Farid N. Najm
169
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ICCAD
2006
IEEE
116views Hardware» more  ICCAD 2006»
16 years 3 months ago
Enhanced error vector magnitude (EVM) measurements for testing WLAN transceivers
As wireless LAN devices become more prevalent in the consumer electronics market, there is an ever increasing pressure to reduce their overall cost. The test cost of such devices ...
Erkan Acar, Sule Ozev, Kevin B. Redmond
ICCAD
2005
IEEE
120views Hardware» more  ICCAD 2005»
16 years 3 months ago
Practical techniques to reduce skew and its variations in buffered clock networks
Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variation...
Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, P...
ICCAD
2004
IEEE
88views Hardware» more  ICCAD 2004»
16 years 3 months ago
Interconnect lifetime prediction under dynamic stress for reliability-aware design
Thermal effects are becoming a limiting factor in highperformance circuit design due to the strong temperaturedependence of leakage power, circuit performance, IC package cost and...
Zhijian Lu, Wei Huang, John Lach, Mircea R. Stan, ...
ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
16 years 3 months ago
Static statistical timing analysis for latch-based pipeline designs
A latch-based timing analyzer is an essential tool for developing high-speed pipeline designs. As process variations increasingly influence the timing characteristics of DSM desi...
Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, San...