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ISMVL
1997
IEEE
99views Hardware» more  ISMVL 1997»
15 years 10 months ago
Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...
Riccardo Mariani, Roberto Roncella, Roberto Salett...
AIIDE
2008
15 years 9 months ago
Automatic Generation of Game Level Solutions as Storyboards
Interactive Storytelling techniques are attracting much interest for their potential to develop new game genres but also as another form of procedural content generation, specific...
David Pizzi, Marc Cavazza, Alex Whittaker, Jean-Lu...
DAC
2009
ACM
16 years 7 months ago
Multicore parallel min-cost flow algorithm for CAD applications
Computational complexity has been the primary challenge of many VLSI CAD applications. The emerging multicore and manycore microprocessors have the potential to offer scalable perf...
Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng
ICS
2005
Tsinghua U.
16 years 4 days ago
Improved automatic testcase synthesis for performance model validation
Performance simulation tools must be validated during the design process as functional models and early hardware are developed, so that designers can be sure of the performance of...
Robert H. Bell Jr., Lizy Kurian John
RTAS
1997
IEEE
15 years 10 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford