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ATS
2003
IEEE
110views Hardware» more  ATS 2003»
15 years 11 months ago
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults
Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of thes...
Yu-Chiun Lin, Shi-Yu Huang
KBSE
2003
IEEE
15 years 11 months ago
Fault Localization With Nearest Neighbor Queries
We present a method for performing fault localization using similar program spectra. Our method assumes the existence of a faulty run and a larger number of correct runs. It then ...
Manos Renieris, Steven P. Reiss
DANCE
2002
IEEE
15 years 11 months ago
Towards an Active Network Architecture
Active networks allow their users to inject customized programs into the nodes of the network. An extreme case, in which we are most interested, replaces packets with “capsulesâ...
David L. Tennenhouse, David Wetherall
DFT
2002
IEEE
79views VLSI» more  DFT 2002»
15 years 11 months ago
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm
We propose an algorithm for gate-delay fault diagnosis. It is based on the inject-and-evaluate paradigm [1], in which the fault site(s) are predicted through a series of injection...
Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang
VTS
2000
IEEE
114views Hardware» more  VTS 2000»
15 years 10 months ago
Detection of CMOS Defects under Variable Processing Conditions
Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points. In this paper, the power supply transient...
Amy Germida, James F. Plusquellic