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» BASE: Using Abstraction to Improve Fault Tolerance
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ISCA
2003
IEEE
136views Hardware» more  ISCA 2003»
15 years 11 months ago
Transient-Fault Recovery for Chip Multiprocessors
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...
Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz,...
ETS
2010
IEEE
150views Hardware» more  ETS 2010»
15 years 7 months ago
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs
It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially ...
Daniel Tille, Stephan Eggersglüß, Rene ...
CCGRID
2008
IEEE
15 years 8 months ago
Using Probabilistic Characterization to Reduce Runtime Faults in HPC Systems
Abstract--The current trend in high performance computing is to aggregate ever larger numbers of processing and interconnection elements in order to achieve desired levels of compu...
Jim M. Brandt, Bert J. Debusschere, Ann C. Gentile...
GLOBECOM
2010
IEEE
15 years 4 months ago
Assessing the Impact of Geographically Correlated Failures on Overlay-Based Data Dissemination
Abstract--This paper addresses reliability of data dissemination applications when there are severe disruptions to the underlying physical infrastructure. Such massive simultaneous...
Kyungbaek Kim, Nalini Venkatasubramanian
INTEGRATION
2006
102views more  INTEGRATION 2006»
15 years 6 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...