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» BASE: Using Abstraction to Improve Fault Tolerance
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ITC
1997
IEEE
129views Hardware» more  ITC 1997»
15 years 10 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
EDCC
2008
Springer
15 years 8 months ago
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
Roman Obermaisser, Hubert Kraut, Christian El Sall...
WIOPT
2005
IEEE
15 years 12 months ago
Analysis of a Distributed Algorithm to Determine Multiple Routes with Path Diversity in Ad Hoc Networks
With multipath routing in mobile ad hoc networks (MANETs), a source can establish multiple routes to a destination for routing data. In MANETs, mulitpath routing can be used to pr...
Stephen Mueller, Dipak Ghosal
IJNSEC
2008
129views more  IJNSEC 2008»
15 years 6 months ago
LAMAIDS: A Lightweight Adaptive Mobile Agent-based Intrusion Detection System
Intrusion detection system (IDS) has become an essential component of a computer security scheme as the number of security-breaking attempts originating inside organizations is in...
Mohamad A. Eid, Hassan Artail, Ayman I. Kayssi, Al...
INFOCOM
2009
IEEE
16 years 1 months ago
MARA: Maximum Alternative Routing Algorithm
—In hop-by-hop networks, provision of multipath routes for all nodes can improve fault tolerance and performance. In this paper we study the multipath route calculation by constr...
Yasuhiro Ohara, Shinji Imahori, Rodney Van Meter