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DAC
2007
ACM
16 years 7 months ago
Modeling the Function Cache for Worst-Case Execution Time Analysis
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
Raimund Kirner, Martin Schoeberl
166
Voted
DAC
2007
ACM
16 years 7 months ago
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation
We present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic-structures and both die-to-die and with...
Khaled R. Heloue, Navid Azizi, Farid N. Najm
DAC
2003
ACM
16 years 7 months ago
Instruction encoding synthesis for architecture exploration using hierarchical processor models
This paper presents a novel instruction encoding generation technique for use in architecture exploration for application specific processors. The underlying exploration methodolo...
Achim Nohl, Volker Greive, Gunnar Braun, Andreas H...
DAC
2005
ACM
16 years 7 months ago
Simulation models for side-channel information leaks
Small, embedded integrated circuits (ICs) such as smart cards are vulnerable to so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power co...
Kris Tiri, Ingrid Verbauwhede
MICCAI
2006
Springer
16 years 7 months ago
An Approach for the Automatic Cephalometric Landmark Detection Using Mathematical Morphology and Active Appearance Models
Cephalometric analysis of lateral radiographs of the head is an important diagnosis tool in orthodontics. Based on manually locating specific landmarks, it is a tedious, time-consu...
Mariano Alcañiz Raya, Sylvia Rueda