302 search results - page 14 / 61 » Automatic Verification of Timed Circuits |
154
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DAC
1996
ACM
15 years 10 months ago
1996
ACM
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
145
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FMCAD
2000
Springer
15 years 9 months ago
2000
Springer
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...
187
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ASYNC
1997
IEEE
15 years 9 months ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...
176
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HASE
1999
IEEE
15 years 10 months ago
1999
IEEE
Statechart Diagrams provide a graphical notation for describing dynamic aspects of system behaviour within the Unified Modeling Language (UML). In this paper we present a branchin...
198
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CL
2008
Springer
15 years 6 months ago
2008
Springer
Currently available application frameworks that target the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for m...