Sciweavers

327 search results - page 55 / 66
» Automatic Array Privatization
Sort
View
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
15 years 11 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
152
Voted
ISMVL
2000
IEEE
121views Hardware» more  ISMVL 2000»
15 years 10 months ago
Evolvable Hardware: From On-Chip Circuit Synthesis to Evolvable Space Systems
Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, comments o...
Adrian Stoica
HPDC
1998
IEEE
15 years 10 months ago
Efficient Coupling of Parallel Applications Using PAWS
PAWS (Parallel Application WorkSpace) is a software infrastructure for use in connecting separate parallel applications within a component-like model. A central PAWS Controller co...
Peter H. Beckman, Patricia K. Fasel, William F. Hu...
185
Voted
FPCA
1993
15 years 10 months ago
Benchmarking Implementations of Lazy Functional Languages
Five implementations of di erent lazy functional languages are compared using a common benchmark of a dozen medium size programs. The benchmarking procedure has been designed such...
Pieter H. Hartel, Koen Langendoen
PLDI
1993
ACM
15 years 10 months ago
Global Optimizations for Parallelism and Locality on Scalable Parallel Machines
Data locality is critical to achievinghigh performance on large-scale parallel machines. Non-local data accesses result in communication that can greatly impact performance. Thus ...
Jennifer-Ann M. Anderson, Monica S. Lam