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ICCD
2006
IEEE
123views Hardware» more  ICCD 2006»
16 years 3 months ago
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug
Abstract— This paper presents techniques that enhance automatically generated hardware assertion checkers to facilitate debugging within the assertion-based verification paradig...
Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
ICCAD
2005
IEEE
121views Hardware» more  ICCAD 2005»
16 years 3 months ago
Transition-by-transition FSM traversal for reachability analysis in bounded model checking
Abstract— In bounded model checking (BMC)-based verification flows lack of reachability constraints often leads to false negatives. At present, it is daily practice of a veri...
Minh D. Nguyen, Dominik Stoffel, Markus Wedler, Wo...
PADL
2010
Springer
16 years 3 months ago
Static Detection of Race Conditions in Erlang
Abstract. We address the problem of detecting some commonly occurring kinds of race conditions in Erlang programs using static analysis. Our analysis is completely automatic, fast ...
Maria Christakis, Konstantinos F. Sagonas
DASFAA
2009
IEEE
126views Database» more  DASFAA 2009»
16 years 1 months ago
Supporting Execution-Level Business Process Modeling with Semantic Technologies
Abstract. When creating execution-level process models from conceptual to-be process models, challenges are to find implementations for process activities and to use these impleme...
Matthias Born, Jörg Hoffmann, Tomasz Kaczmare...
VLSID
2009
IEEE
182views VLSI» more  VLSID 2009»
16 years 1 months ago
Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design
Abstract— This paper introduces a fuzzy logic based guidance architecture to a graph grammar framework for automated design of analog circuits. The grammar generates circuit topo...
Angan Das, Ranga Vemuri