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195
Voted
DAC
2004
ACM
16 years 7 months ago
Refining the SAT decision ordering for bounded model checking
Bounded Model Checking (BMC) relies on solving a sequence of highly correlated Boolean satisfiability (SAT) problems, each of which corresponds to the existence of counter-example...
Chao Wang, HoonSang Jin, Gary D. Hachtel, Fabio So...
200
Voted
DAC
2005
ACM
16 years 7 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
DAC
2005
ACM
16 years 7 months ago
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology
In this paper, we describe FLEXBUS, a flexible, high-performance onchip communication architecture featuring a dynamically configurable topology. FLEXBUS is designed to detect run...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
DAC
2006
ACM
16 years 7 months ago
A family of cells to reduce the soft-error-rate in ternary-CAM
Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These eve...
Navid Azizi, Farid N. Najm
DAC
2006
ACM
16 years 7 months ago
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming
In this paper, we propose an exact algorithm for the problem of area optimization under a delay constraint in the synthesis of multiplierless FIR filters. To the best of our knowl...
Eduardo A. C. da Costa, José Monteiro, Leve...