Sciweavers

4359 search results - page 528 / 872
» Automated Pipeline Design
Sort
View
DAC
2007
ACM
16 years 7 months ago
Modeling the Function Cache for Worst-Case Execution Time Analysis
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
Raimund Kirner, Martin Schoeberl
DAC
2007
ACM
16 years 7 months ago
An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration
The bus tracing is used to catch related signals for further investigation and analysis. However, the trace size of cycleaccurate tracing is large and the trace cycle is shallow u...
Chung-Fu Kao, Ing-Jer Huang, Chi-Hung Lin
190
Voted
DAC
2007
ACM
16 years 7 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
DAC
2007
ACM
16 years 7 months ago
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations
Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis has become essential. We present a novel method for post-silicon analysis that g...
Qunzeng Liu, Sachin S. Sapatnekar
DAC
1998
ACM
16 years 7 months ago
Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems
An embedded system the system continuously interacts with its environment under strict timing constraints, called the external constraints, and it is important to know how these e...
Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta