4359 search results - page 510 / 872 » Automated Pipeline Design |
165
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presente...
135
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors c...
190
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
172
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DAC
2001
ACM
16 years 7 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
156
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DAC
2001
ACM
16 years 7 months ago
2001
ACM
This paper describes the first application of the Genevieve test generation methodology. The Genevieve approach uses semi-formal techniques derived from "model-checking"...