Sciweavers

4359 search results - page 464 / 872
» Automated Pipeline Design
Sort
View
ISPD
2004
ACM
134views Hardware» more  ISPD 2004»
16 years 8 days ago
Performance-driven register insertion in placement
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
Dennis K. Y. Tong, Evangeline F. Y. Young
PACS
2004
Springer
115views Hardware» more  PACS 2004»
16 years 6 days ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
SAMOS
2004
Springer
16 years 6 days ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
SIGGRAPH
1998
ACM
15 years 11 months ago
Realistic Modeling and Rendering of Plant Ecosystems
Modeling and rendering of natural scenes with thousands of plants poses a number of problems. The terrain must be modeled and plants must be distributed throughout it in a realist...
Oliver Deussen, Pat Hanrahan, Bernd Lintermann, Ra...
ARITH
1993
IEEE
15 years 11 months ago
Fast implementations of RSA cryptography
We detail and analyse the critical techniques which may be combined in the design of fast hardware for RSA cryptography: chinese remainders, star chains, Hensel's odd divisio...
Mark Shand, Jean Vuillemin