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DAC
2004
ACM
16 years 7 months ago
Toward a systematic-variation aware timing methodology
Variability of circuit performance is becoming a very important issue for ultra-deep sub-micron technology. Gate length variation has the most direct impact on circuit performance...
Puneet Gupta, Fook-Luen Heng
DAC
2005
ACM
16 years 7 months ago
Full-chip analysis of leakage power under process variations, including spatial correlations
In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correla...
Hongliang Chang, Sachin S. Sapatnekar
DAC
2005
ACM
16 years 7 months ago
Power-aware placement
Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activity-based register c...
Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sher...
DAC
2005
ACM
16 years 7 months ago
Architecture-adaptive range limit windowing for simulated annealing FPGA placement
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
Kenneth Eguro, Scott Hauck, Akshay Sharma
155
Voted
DAC
2005
ACM
16 years 7 months ago
A quasi-convex optimization approach to parameterized model order reduction
In this paper an optimization based model order reduction (MOR) framework is proposed. The method involves setting up a quasiconvex program that explicitly minimizes a relaxation ...
Kin Cheong Sou, Alexandre Megretski, Luca Daniel