Variability of circuit performance is becoming a very important issue for ultra-deep sub-micron technology. Gate length variation has the most direct impact on circuit performance...
In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correla...
Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activity-based register c...
Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sher...
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
In this paper an optimization based model order reduction (MOR) framework is proposed. The method involves setting up a quasiconvex program that explicitly minimizes a relaxation ...