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ISCA
2003
IEEE
144views Hardware» more  ISCA 2003»
16 years 5 days ago
Half-Price Architecture
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
Ilhyun Kim, Mikko H. Lipasti
MTV
2003
IEEE
109views Hardware» more  MTV 2003»
16 years 5 days ago
A Methodology for Validation of Microprocessors using Equivalence Checking
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Nikil D. Dutt
SIGUCCS
2003
ACM
16 years 4 days ago
Instructional support at small universities: a training perspective
This paper intends to present the challenges and opportunities encountered in technology training at small institutions using Trinity University as a case in point. During the cou...
Vidya Ananthanarayanan, Judith Reiffert
FPL
2003
Springer
95views Hardware» more  FPL 2003»
16 years 3 days ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
15 years 12 months ago
Data marshaling for multi-core architectures
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
M. Aater Suleman, Onur Mutlu, José A. Joao,...