4359 search results - page 396 / 872 » Automated Pipeline Design |
198
click to vote
EUROPAR
2005
Springer
16 years 12 days ago
2005
Springer
Dynamic instruction scheduling logic is one of the most critical and cycle-limiting structures in modern superscalar processors, and it is not easily pipelined without significant ...
178
click to vote
IWANN
2005
Springer
16 years 11 days ago
2005
Springer
In this paper, a fully functional prototype of an asynchronous 4-to-4 Address Event Representation (AER) mapper is presented. AER is an event driven communication protocol original...
184
click to vote
ACMMSP
2004
ACM
16 years 9 days ago
2004
ACM
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
145
click to vote
ASPDAC
2004
ACM
16 years 9 days ago
2004
ACM
– A low-power graphics LSI is designed and implemented for mobile multimedia applications. The LSI contains a 32bit RISC processor with enhanced MAC, a 3D rendering engine, progr...
178
click to vote
SENSYS
2004
ACM
16 years 9 days ago
2004
ACM
Reprogramming of sensor networks is an important and challenging problem as it is often necessary to reprogram the sensors in place. In this paper, we propose a multihop reprogram...