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IEEEPACT
2006
IEEE
16 years 28 days ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev
IPPS
2006
IEEE
16 years 27 days ago
Accelerating DTI tractography using FPGAs
Diffusion Tensor Imaging (DTI) tractography in Magnetic Resonance Imaging (MRI) is a computationally intensive procedure, requiring on the order of tens of minutes to complete tr...
Kwatra Kwatra, Viktor K. Prasanna, Mitali Singh
ISPASS
2006
IEEE
16 years 27 days ago
Comparing simulation techniques for microarchitecture-aware floorplanning
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
ANCS
2006
ACM
16 years 26 days ago
A practical fast parallel routing architecture for Clos networks
Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos network...
Si-Qing Zheng, Ashwin Gumaste, Enyue Lu
ISLPED
2006
ACM
100views Hardware» more  ISLPED 2006»
16 years 25 days ago
Selective writeback: exploiting transient values for energy-efficiency and performance
Today’s superscalar microprocessors use large, heavily-ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of ...
Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev,...