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152
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ISQED
2009
IEEE
187views Hardware» more  ISQED 2009»
16 years 1 months ago
An efficient current-based logic cell model for crosstalk delay analysis
 Electrical Modeling for High Bandwidth IO Link  Chirayu Amin, Chandramouli Kashyap ¬ Intel Corp., Hillsboro, OR  Prateek Bhansali ¬ Univ. of Minnesota, Mi...
Debasish Das, William Scott, Shahin Nazarian, Hai ...
FCCM
2008
IEEE
160views VLSI» more  FCCM 2008»
16 years 1 months ago
Facilitating Processor-Based DPR Systems for non-DPR Experts
Currently, only Xilinx Field Programmable Gate Arrays (FPGAs) support Dynamic Partial Reconfiguration (DPR). While there is currently some Computer Aided Design (CAD) tool support...
Edward Chen, William A. Gruver, Dorian Sabaz, Lesl...
178
Voted
FASE
2006
Springer
15 years 10 months ago
: Designing a Scalable Build Process
Modern software codebases are frequently large, heterogeneous, and constantly evolving. The languages and tools for software construction, including code builds and configuration m...
Jason Hickey, Aleksey Nogin
GLVLSI
2007
IEEE
140views VLSI» more  GLVLSI 2007»
16 years 1 months ago
Structured and tuned array generation (STAG) for high-performance random logic
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
ICRA
1995
IEEE
156views Robotics» more  ICRA 1995»
15 years 10 months ago
Assembly maintainability Study with Motion Planning
Maintainability is an important issue in design where the accessibility of certain parts is determined for routine maintenance. In the past its study has been largely manual and l...
Hsuan Chang, Tsai-Yen Li