4359 search results - page 355 / 872 » Automated Pipeline Design |
163
click to vote
ICIP
2003
IEEE
16 years 8 months ago
2003
IEEE
This paper describes a new co-processor architecture designed for CMOS sensor imaging. The co-processor unit is integrated into the image acquisition loop so as to exploit the ful...
183
click to vote
HPCA
2003
IEEE
16 years 7 months ago
2003
IEEE
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
179
click to vote
ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
164
click to vote
DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—Packet-switched interconnect fabric is a promising on-chip communication solution for many-core architectures. It offers high throughput and excellent scalability for on-chip da...
172
click to vote
GLVLSI
2009
IEEE
16 years 1 months ago
2009
IEEE
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power im...