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Automated Pipeline Design
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Task generation and compile-time scheduling for mixed data-control embedded software
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YAPI: application modeling for signal processing systems
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Erwin A. de Kock, W. J. M. Smits, Pieter van der W...
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Tools or users: which is the bigger bottleneck?
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vlsicad.ucsd.edu
Andrew B. Kahng, Ronald Collett, Patrick Groenevel...
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Enhancing test efficiency for delay fault testing using multiple-clocked schemes
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Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jenni...
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DAC
2005
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Navigating registers in placement for clock network minimization
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Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qian...
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