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DATE
2006
IEEE
127views Hardware» more  DATE 2006»
16 years 23 days ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...
SMI
2005
IEEE
156views Image Analysis» more  SMI 2005»
16 years 9 days ago
Visualization of Point-Based Surfaces with Locally Reconstructed Subdivision Surfaces
Point-based surfaces (i.e. surfaces represented by discrete point sets which are either directly obtained by current 3D acquisition devices or converted from other surface represe...
Tamy Boubekeur, Patrick Reuter, Christophe Schlick
FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
16 years 3 days ago
In-system FPGA prototyping of an itanium microarchitecture
We describe an effort to prototype an Itanium microarchitecture using an FPGA. The microarchitecture model is written in the Bluespec hardware description language (HDL) and suppo...
Roland E. Wunderlich, James C. Hoe
139
Voted
ICCSA
2003
Springer
15 years 12 months ago
Computational Modelling of Particle Degradation in Dilute Phase Pneumatic Conveyors
The aim of this paper is to develop a mathematical model with the ability to predict particle degradation during dilute phase pneumatic conveying. A numerical procedure, based on a...
Pierre Chapelle, Nicholas Christakis, Hadi Abou-Ch...
DATE
2000
IEEE
83views Hardware» more  DATE 2000»
15 years 11 months ago
Wave Steered FSMs
In this paper we address the problem of designing very high throughput finite state machines (FSMs). The presence of loops in sequential circuits prevents a straightforward and g...
Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-...