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ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
15 years 4 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
ERSA
2009
146views Hardware» more  ERSA 2009»
15 years 4 months ago
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chal...
ICCD
2007
IEEE
215views Hardware» more  ICCD 2007»
16 years 3 months ago
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li...
LOPSTR
1997
Springer
15 years 10 months ago
A Multi-level Approach to Program Synthesis
Abstract. We present an approach to a coherent program synthesis system which integrates a variety of interactively controlled and automated techniques from theorem proving and alg...
Wolfgang Bibel, Daniel S. Korn, Christoph Kreitz, ...
CVPR
2007
IEEE
16 years 8 months ago
Towards Automatic Photometric Correction of Casually Illuminated Documents
Creating uniform lighting for archival-quality document acquisition remains a non-trivial problem. We propose a novel method for automatic photometric correction of nonplanar docu...
George V. Landon, Yun Lin, W. Brent Seales