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    CLUSTER
    2000
    IEEE
    98views Distributed And Parallel Com...» more  CLUSTER 2000»
    Design and Performance of Maestro Cluster Network
    15 years 11 months ago
    Design and Performance of Maestro Cluster Network
    Download  www.pdmfc.com
    Most clusters so far have used WAN or LAN-based network products for communication due to their market availability. However, they do not always match communication patterns in cl...
    Shinichi Yamagiwa, Munehiro Fukuda, Koichi Wada
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    DAC
    2008
    ACM
    124views Computer Architecture» more  DAC 2008»
    Design and CAD for 3D integrated circuits
    16 years 7 months ago
    Design and CAD for 3D integrated circuits
    Download  www.ece.ncsu.edu
    Ben Shani, Eun Chu Oh, Kurt Obermiller, Michael St...
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    DAC
    1999
    ACM
    112views Computer Architecture» more  DAC 1999»
    Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software
    16 years 7 months ago
    Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software
    Download  ics.kaist.ac.kr
    Hoon Choi, Ju Hwan Yi, Jong-Yeol Lee, In-Cheol Par...
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    DAC
    2003
    ACM
    128views Computer Architecture» more  DAC 2003»
    Schedulers as model-based design elements in programmable heterogeneous multiprocessors
    16 years 7 months ago
    Schedulers as model-based design elements in programmable heterogeneous multiprocessors
    Download  www.ece.cmu.edu
    JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Jos...
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    ISVLSI
    2007
    IEEE
    232views VLSI» more  ISVLSI 2007»
    DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
    16 years 24 days ago
    DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
    Download  www.ece.uvic.ca
    — We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
    Nainesh Agarwal, Nikitas J. Dimopoulos
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