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DAC
2010
ACM
15 years 4 months ago
SCEMIT: a systemc error and mutation injection tool
As high-level models in C and SystemC are increasingly used for verification and even design (through high-level synthesis) of electronic systems, there is a growing need for com...
Peter Lisherness, Kwang-Ting (Tim) Cheng
ISCAS
2006
IEEE
86views Hardware» more  ISCAS 2006»
16 years 4 days ago
Fast timing analysis of plane circuits via two-layer CNN-based modeling
Abstract— A fast timing analysis of plane circuits via two-layer CNNbased modeling, which is necessary for the solution of power/signal integrity problems in printed circuit boar...
Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifum...
JGAA
2006
100views more  JGAA 2006»
15 years 6 months ago
Orthogonal Hypergraph Drawing for Improved Visibility
Visualization of circuits is an important research area in electronic design automation. One commonly accepted method to visualize a circuit aligns the gates to layers and uses or...
Thomas Eschbach, Wolfgang Günther, Bernd Beck...
DAC
2004
ACM
16 years 7 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
DAC
2006
ACM
16 years 7 months ago
An efficient retiming algorithm under setup and hold constraints
In this paper we present a new efficient algorithm for retiming sequential circuits with edge-triggered registers under both setup and hold constraints. Compared with the previous...
Chuan Lin, Hai Zhou