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» Attacks on Steganographic Systems
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DATE
2007
IEEE
92views Hardware» more  DATE 2007»
16 years 22 days ago
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller ...
Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Ch...
IPCCC
2007
IEEE
16 years 20 days ago
First Responders' Crystal Ball: How to Scry the Emergency from a Remote Vehicle
Successes and failures during rescue operations after hurricane Katrina and the Twin Towers attack demonstrated the importance of supporting first responders with adequate means t...
Marco Roccetti, Mario Gerla, Claudio E. Palazzi, S...
KBSE
2007
IEEE
16 years 20 days ago
Checking threat modeling data flow diagrams for implementation conformance and security
Threat modeling analyzes how an adversary might attack a system by supplying it with malicious data or interacting with it. The analysis uses a Data Flow Diagram (DFD) to describe...
Marwan Abi-Antoun, Daniel Wang, Peter Torr
SRDS
2007
IEEE
16 years 19 days ago
The Fail-Heterogeneous Architectural Model
Fault tolerant distributed protocols typically utilize a homogeneous fault model, either fail-crash or fail-Byzantine, where all processors are assumed to fail in the same manner....
Marco Serafini, Neeraj Suri
FPL
2007
Springer
105views Hardware» more  FPL 2007»
16 years 16 days ago
Time Predictable CPU and DMA Shared Memory Access
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...
Christof Pitter, Martin Schoeberl