Sciweavers

16206 search results - page 2907 / 3242
» At Issue
Sort
View
ISCA
2003
IEEE
150views Hardware» more  ISCA 2003»
15 years 12 months ago
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Dan Ernst, Andrew Hamel, Todd M. Austin
ISCA
2003
IEEE
157views Hardware» more  ISCA 2003»
15 years 12 months ago
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
Michael D. Powell, T. N. Vijaykumar
ISCA
2003
IEEE
108views Hardware» more  ISCA 2003»
15 years 12 months ago
Effective ahead Pipelining of Instruction Block Address Generation
On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per c...
André Seznec, Antony Fraboulet
ISCAS
2003
IEEE
167views Hardware» more  ISCAS 2003»
15 years 12 months ago
The multi-level paradigm for distributed fault detection in networks with unreliable processors
In this paper, we study the effectiveness of the multilevel paradigm in considerably reducing the diagnosis latency of distributed algorithms for fault detection in networks with ...
Krishnaiyan Thulasiraman, Ming-Shan Su, V. Goel
ISCC
2003
IEEE
153views Communications» more  ISCC 2003»
15 years 12 months ago
Fuzzy Explicit Marking for Congestion Control in Differentiated Services Networks
This paper presents a new active queue management scheme, Fuzzy Explicit Marking (FEM), implemented within the differentiated services (Diff-Serv) framework to provide congestion ...
Chrysostomos Chrysostomou, Andreas Pitsillides, Ge...
« Prev « First page 2907 / 3242 Last » Next »