To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per c...
In this paper, we study the effectiveness of the multilevel paradigm in considerably reducing the diagnosis latency of distributed algorithms for fault detection in networks with ...
This paper presents a new active queue management scheme, Fuzzy Explicit Marking (FEM), implemented within the differentiated services (Diff-Serv) framework to provide congestion ...
Chrysostomos Chrysostomou, Andreas Pitsillides, Ge...