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FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
16 years 3 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
VL
2009
IEEE
187views Visual Languages» more  VL 2009»
16 years 1 months ago
Changing euler diagram properties by edge transformation of euler dual graphs
Euler diagrams form the basis of several visual modelling notations, including statecharts and constraint diagrams. Recently, various techniques for automated Euler diagram drawin...
John Howse, Peter Rodgers, Gem Stapleton
TOOLS
2008
IEEE
16 years 1 months ago
Component Reassembling and State Transfer in MaDcAr-Based Self-adaptive Software
In this paper, we introduce MaDcAr, a model of engines for dynamic and automatic (re)assembling of component-based software. In MaDcAr, an application description consists of the d...
Guillaume Grondin, Noury Bouraqadi, Laurent Vercou...
MODELS
2007
Springer
16 years 24 days ago
Statechart Development Beyond WYSIWYG
Modeling systems based on semi-formal graphical formalisms, such as Statecharts, have become standard practice in the design of reactive embedded devices. Statecharts are often mor...
Steffen Prochnow, Reinhard von Hanxleden
RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
16 years 7 days ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...