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DATE
2010
IEEE
149views Hardware» more  DATE 2010»
15 years 11 months ago
Efficient decision ordering techniques for SAT-based test generation
Model checking techniques are promising for automated generation of directed tests. However, due to the prohibitively large time and resource requirements, conventional model chec...
Mingsong Chen, Xiaoke Qin, Prabhat Mishra
ASPDAC
1999
ACM
116views Hardware» more  ASPDAC 1999»
15 years 11 months ago
An Automatic Router for the Pin Grid Array Package
A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on...
Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chi...
DATE
1999
IEEE
123views Hardware» more  DATE 1999»
15 years 11 months ago
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length
Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column ...
Manuel Martínez, Maria J. Avedillo, Jos&eac...
ISPD
1999
ACM
106views Hardware» more  ISPD 1999»
15 years 11 months ago
Timing driven maze routing
—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
Sung-Woo Hur, Ashok Jagannathan, John Lillis
ECRTS
1999
IEEE
15 years 11 months ago
Improved scheduling of control tasks
The paper considers the implementation of digital controllers as real-time tasks in priority-preemptive systems. The performance of a digital feedback control system depends criti...
Anton Cervin