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» Assessing Architectural Complexity
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VLSID
2004
IEEE
108views VLSI» more  VLSID 2004»
16 years 7 months ago
Boolean Decomposition Using Two-literal Divisors
This paper is an attempt to answer the following question: how much improvement can be obtained in logic decomposition by using Boolean divisors? Traditionally, the existence of t...
Nilesh Modi, Jordi Cortadella
VLSID
2003
IEEE
253views VLSI» more  VLSID 2003»
16 years 7 months ago
High Level Synthesis from Sim-nML Processor Models
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
Souvik Basu, Rajat Moona
VLSID
2003
IEEE
148views VLSI» more  VLSID 2003»
16 years 7 months ago
Extending Platform-Based Design to Network on Chip Systems
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
Juha-Pekka Soininen, Axel Jantsch, Martti Forsell,...
HPCA
2001
IEEE
16 years 7 months ago
Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors
The performance of out-of-order processors increases with the instruction window size. In conventional processors, the effective instruction window cannot be larger than the issue...
Pierre Michaud, André Seznec
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
16 years 3 months ago
Extending the Applicability of Parallel-Serial Scan Designs
Although scan-based designs are widely used in order to reduce the complexity of test generation, test application time and test data volume are substantially increased. We propos...
Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu