Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...
Abstract. Grid computing has great potential for supporting the integration of complex, fast changing biological data repositories to enable distributed data analysis. One scenario...
Lucas Zamboulis, Hao Fan, Khalid Belhajjame, Jenni...
Ad hoc networks are a type of computational system whose members may fail to, or choose not to, comply with the laws governing their behaviour. We are investigating to what extent ...