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» Assessing Architectural Complexity
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DAC
2009
ACM
15 years 10 months ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen
APCSAC
2004
IEEE
15 years 10 months ago
A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking
As device sizes continue shrinking, lower charges are needed to activate gates, and consequently ever smaller external events (such as single ionizing particles of naturally occurr...
Xiaobin Li, Jean-Luc Gaudiot
DAC
2004
ACM
15 years 10 months ago
Communication-efficient hardware acceleration for fast functional simulation
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong...
DAC
2004
ACM
15 years 10 months ago
Quadratic placement using an improved timing model
The performance of timing-driven placement methods depends strongly on the choice of the net model. In this paper a more precise net model is presented that does not increase nume...
Bernd Obermeier, Frank M. Johannes
DAC
2004
ACM
15 years 10 months ago
An SoC design methodology using FPGAs and embedded microprocessors
In System on Chip (SoC) design, growing design complexity has esigners to start designs at higher abstraction levels. This paper proposes an SoC design methodology that makes full...
Nobuyuki Ohba, Kohji Takano