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» Assessing Architectural Complexity
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NOCS
2007
IEEE
16 years 1 months ago
Transaction-Based Communication-Centric Debug
Abstract— The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC...
Kees Goossens, Bart Vermeulen, Remco van Steeden, ...
CODES
2004
IEEE
15 years 10 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
IADIS
2004
15 years 8 months ago
Moginma: an autonomous grid node monitoring agent
The accelerated development in grid computing has positioned it as a promising next generation computing platform. It enables the creation of virtual organizations (VO) for sharin...
Arshad Ali, Fawad Nazir, Hamid Abbas Burki, Tallat...
IM
2003
15 years 8 months ago
Facilitating Efficient and Reliable Monitoring through HAMSA
: Monitoring is a fundamental building block of any network management system. It is needed to ensure that the network operates within the required parameters, and to account for u...
David Breitgand, Danny Dolev, Danny Raz, Gleb Shav...
SIGARCH
2008
107views more  SIGARCH 2008»
15 years 6 months ago
A lightweight streaming layer for multicore execution
As multicore architectures gain widespread use, it becomes increasingly important to be able to harness their additional processing power to achieve higher performance. However, e...
David Zhang, Qiuyuan J. Li, Rodric Rabbah, Saman A...