Sciweavers

4287 search results - page 398 / 858
» Assessing Architectural Complexity
Sort
View
DAC
1996
ACM
15 years 11 months ago
Bit-Level Analysis of an SRT Divider Circuit
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
Randal E. Bryant
DAC
1996
ACM
15 years 11 months ago
Sizing of Clock Distribution Networks for High Performance CPU Chips
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
Madhav P. Desai, Radenko Cvijetic, James Jensen
DAC
1996
ACM
15 years 11 months ago
RTL Emulation: The Next Leap in System Verification
ion. Production use of text-based methodology has enabled designers to capture designs of hundreds of thousands of gates using graphic ESDA tools. Source: Data Quest (Verilog/VHDL ...
Sanjay Sawant, Paul Giordano
PARLE
1992
15 years 11 months ago
Performance Evaluation of Parallel Transaction Processing in Shared Nothing Database Systems
Complex and data-intensive database queries mandate parallel processing strategies to achieve sufficiently short response times. In praxis, parallel database processing is mostly b...
Robert Marek, Erhard Rahm
CCS
2009
ACM
15 years 10 months ago
The bayesian traffic analysis of mix networks
This work casts the traffic analysis of anonymity systems, and in particular mix networks, in the context of Bayesian inference. A generative probabilistic model of mix network ar...
Carmela Troncoso, George Danezis