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DAC
1999
ACM
15 years 11 months ago
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar...
ANCS
2007
ACM
15 years 10 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
COMSWARE
2006
IEEE
15 years 10 months ago
Architecting protocol stack optimizations on mobile devices
Applications using traditional protocol stacks (e.g TCP/IP) from wired networks do not function efficiently in mobile wireless scenarios. This is primarily due to the layered archi...
Vijay T. Raisinghani, Sridhar Iyer
CP
2008
Springer
15 years 8 months ago
An Application of Constraint Programming to Superblock Instruction Scheduling
Modern computer architectures have complex features that can only be fully taken advantage of if the compiler schedules the compiled code. A standard region of code for scheduling ...
Abid M. Malik, Michael Chase, Tyrel Russell, Peter...
DAC
2012
ACM
13 years 9 months ago
Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse
Due to the breakdown of Dennardian scaling, the percentage of a silicon chip that can switch at full frequency is dropping exponentially with each process generation. This utiliza...
Michael B. Taylor