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FPL
2004
Springer
74views Hardware» more  FPL 2004»
16 years 2 days ago
A Structured Methodology for System-on-an-FPGA Design
Abstract. Increasing logic resources coupled with a proliferation of integrated performance enhancing primitives in high-end FPGAs results in an increased design complexity which r...
N. Pete Sedcole, Peter Y. K. Cheung, George A. Con...
ASAP
2003
IEEE
108views Hardware» more  ASAP 2003»
15 years 12 months ago
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
Terry Tao Ye, Giovanni De Micheli
DAC
1997
ACM
15 years 11 months ago
Hierarchical Sequence Compaction for Power Estimation
- This paper presents an effective technique for compacting a large sequence of input vectors into a much smaller one such that when the two sequences are applied to any circuit, t...
Radu Marculescu, Diana Marculescu, Massoud Pedram
DAC
1996
ACM
15 years 10 months ago
Efficient Approximation Algorithms for Floorplan Area Minimization
Approximation has been shown to be an eective method for reducing the time and space costs of solving various oorplan area minimization problems. In this paper, we present several...
Danny Z. Chen, Xiaobo Hu
DAC
1994
ACM
15 years 10 months ago
BDD Variable Ordering for Interacting Finite State Machines
We address the problem of obtaining good variable orderings for the BDD representation of a system of interacting finite state machines (FSMs). Orderings are derived from the comm...
Adnan Aziz, Serdar Tasiran, Robert K. Brayton