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» Assessing Architectural Complexity
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DASIP
2010
15 years 1 months ago
Hardware code generation from dataflow programs
The elaboration of new systems on embedded targets is becoming more and more complex. In particular, multimedia devices are now implemented using mixed hardware and software archi...
Nicolas Siret, Matthieu Wipliez, Jean-Franç...
155
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CGO
2009
IEEE
16 years 1 months ago
OptiScope: Performance Accountability for Optimizing Compilers
Compilers employ many aggressive code transformations to achieve highly optimized code. However, because of complex target architectures and unpredictable optimization interaction...
Tipp Moseley, Dirk Grunwald, Ramesh Peri
ICNP
2009
IEEE
16 years 1 months ago
Better by a HAIR: Hardware-Amenable Internet Routing
—Routing protocols are implemented in the form of software running on a general-purpose microprocessor. However, conventional software-based router architectures face significan...
Firat Kiyak, Brent Mochizuki, Eric Keller, Matthew...
ETS
2010
IEEE
174views Hardware» more  ETS 2010»
15 years 7 months ago
Test-architecture optimization for TSV-based 3D stacked ICs
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakr...
ISCAS
2007
IEEE
93views Hardware» more  ISCAS 2007»
16 years 29 days ago
VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding
Abstract— This paper describes the first VLSI implementation of lattice reduction (LR) aided multi-antenna broadcast precoding with vector perturbation. The considered LR scheme...
Andreas Burg, Dominik Seethaler, Gerald Matz