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DATE
2007
IEEE
156views Hardware» more  DATE 2007»
16 years 26 days ago
Process variation tolerant low power DCT architecture
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
Nilanjan Banerjee, Georgios Karakonstantis, Kaushi...
ICDCS
2009
IEEE
15 years 4 months ago
The Case for Spam-Aware High Performance Mail Server Architecture
The email volume per mailbox has largely remained low and unchanged in the past several decades, and hence mail server performance has largely remained a secondary issue. The stee...
Abhinav Pathak, Syed Ali Raza Jafri, Y. Charlie Hu
ICVS
2001
Springer
15 years 11 months ago
A Modular Software Architecture for Real-Time Video Processing
An increasing number of computer vision applications require on-line processing of data streams, preferably in real-time. This trend is fueled by the mainstream availability of low...
Alexandre R. J. François, Gérard G. ...
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
15 years 11 months ago
Tarantula: A Vector Extension to the Alpha Architecture
Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processo...
Roger Espasa, Federico Ardanaz, Julio Gago, Roger ...
CN
2007
114views more  CN 2007»
15 years 6 months ago
BiSNET: A biologically-inspired middleware architecture for self-managing wireless sensor networks
This paper describes BiSNET (Biologically-inspired architecture for Sensor NETworks), a middleware architecture that addresses several key issues in multi-modal wireless sensor ne...
Pruet Boonma, Junichi Suzuki