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JCO
2011
115views more  JCO 2011»
15 years 1 months ago
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
Chen Liao, Shiyan Hu
PARA
2000
Springer
15 years 10 months ago
JavaGrande - High Performance Computing with Java
The JavaGrande Forum is a group of users, researchers, and interested parties from industry. The Forum members are either trying to use Java for resource-intensive applications or ...
Michael Philippsen, Ronald F. Boisvert, Vladimir G...
DAC
2006
ACM
16 years 7 months ago
Optimal cell flipping in placement and floorplanning
In a placed circuit, there are a lot of movable cells that can be flipped to further reduce the total wirelength, without affecting the original placement solution. We aim at solv...
Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N...
ICSE
2008
IEEE-ACM
16 years 7 months ago
Symbolic mining of temporal specifications
Program specifications are important in many phases of the software development process, but they are often omitted or incomplete. An important class of specifications takes the f...
Mark Gabel, Zhendong Su
ICS
2009
Tsinghua U.
16 years 1 months ago
High-performance CUDA kernel execution on FPGAs
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
Alexandros Papakonstantinou, Karthik Gururaj, John...