3943 search results - page 466 / 789 » Architecture-Level Requirements Specification |
158
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
148
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DAC
2008
ACM
16 years 7 months ago
2008
ACM
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
163
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating interna...
162
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Langua...
162
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
Physical phenomena such as temperature have an increasingly important role in performance and reliability of modern process technologies. This trend will only strengthen with futu...