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VLSID
1999
IEEE
91views VLSI» more  VLSID 1999»
15 years 11 months ago
Timed Circuit Synthesis Using Implicit Methods
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...
Robert Thacker, Wendy Belluomini, Chris J. Myers
ICCAD
1998
IEEE
120views Hardware» more  ICCAD 1998»
15 years 11 months ago
Communication synthesis for distributed embedded systems
Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing desi...
Ross B. Ortega, Gaetano Borriello
CHI
1998
ACM
15 years 10 months ago
The Vista Environment for the Coevolutionary Design of User Interfaces
User centered design requires the creation of numerous design artifacts such as task hierarchy, task-oriented specification, user interface design, architecture design and code. I...
Judy Brown, T. C. Nicholas Graham, Timothy N. Wrig...
ICCAD
1994
IEEE
65views Hardware» more  ICCAD 1994»
15 years 10 months ago
Incremental formal design verification
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
Gitanjali Swamy, Robert K. Brayton
ITC
1993
IEEE
110views Hardware» more  ITC 1993»
15 years 10 months ago
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A...