Sciweavers

3943 search results - page 171 / 789
» Architecture-Level Requirements Specification
Sort
View
ISCAS
2005
IEEE
153views Hardware» more  ISCAS 2005»
16 years 4 days ago
A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher
—A high-throughput hardware architecture and FPGA implementation of the 64-bit NESSIE proposal, MISTY1 block cipher, is presented in this paper. This architecture, in contrast to...
Paris Kitsos, Michalis D. Galanis, Odysseas G. Kou...
EMISA
2005
Springer
16 years 3 days ago
From Reference Model to Component Model
Stable component models are an essential prerequisite for developing customer-individual business applications. Thereby the information for the identification and specification of ...
Antonia Albani, Johannes Maria Zaha
ICESS
2005
Springer
16 years 2 days ago
Self-correction of FPGA-Based Control Units
This paper presents a self-correcting control unit design using Hamming codes for finite state machine (FSM) state encoding. The adopted technique can correct single-bit errors and...
Iouliia Skliarova
OTM
2005
Springer
16 years 1 days ago
An Approach for Semantic Query Processing with UDDI
UDDI is not suitable for handling semantic markups for Web services due to its flat data model and limited search capabilities. In this paper, we introduce an approach to allow for...
Jim Luo, Bruce E. Montrose, Myong H. Kang
ICSR
2004
Springer
15 years 12 months ago
Framed Aspects: Supporting Variability and Configurability for AOP
Aspect oriented programming (AOP) seeks to decompose concerns which crosscut system structure into more manageable modules. However, current AOP techniques alone lack the configura...
Neil Loughran, Awais Rashid