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INTEGRATION
2008
127views more  INTEGRATION 2008»
15 years 5 months ago
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, And...
INFOCOM
2012
IEEE
13 years 9 months ago
RISA: Distributed Road Information Sharing Architecture
—With the advent of the new IEEE 802.11p DSRC/WAVE radios, Vehicle-to-Vehicle (V2V) communications is poised for a dramatic leap. A canonical application for these future vehicul...
Joon Ahn, Yi Wang, Bo Yu, Fan Bai, Bhaskar Krishna...
ASPDAC
2004
ACM
101views Hardware» more  ASPDAC 2004»
16 years 6 days ago
A sub-mW MPEG-4 motion estimation processor core for mobile video application
This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a Gradient Descent Search algorithm whose computation power is only 7% of the...
Yuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, K...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
16 years 1 months ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...
ISMAR
2007
IEEE
16 years 1 months ago
A System Architecture for Ubiquitous Tracking Environments
Ubiquitous tracking setups, covering large tracking areas with many heterogeneous sensors of varying accuracy, require dedicated middleware to facilitate development of stationary...
Manuel Huber, Daniel Pustka, Peter Keitler, Floria...