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FCCM
2009
IEEE
123views VLSI» more  FCCM 2009»
15 years 10 months ago
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
Hoang Le, Viktor K. Prasanna
GLOBECOM
2009
IEEE
15 years 10 months ago
Scalable Support of Interdomain Routes in a Single AS
In this paper, we show a prototype implementation for a new architecture of supporting interdomain routes. It is widely recognized that the rapid growth of Internet is forcing a sc...
Cristel Pelsser, Akeo Masuda, Kohei Shiomoto
DAC
2010
ACM
15 years 7 months ago
Virtual channels vs. multiple physical networks: a comparative analysis
Packet-switched networks-on-chip (NoC) have been proposed as an efficient communication infrastructure for multi-core architectures. Adding virtual channels to a NoC helps to avoi...
Young-Jin Yoon, Nicola Concer, Michele Petracca, L...
DAC
2000
ACM
16 years 7 months ago
Performance analysis and optimization of latency insensitive systems
Latency insensitive design has been recently proposed in literature as a way to design complex digital systems, whose functional behavior is robust with respect to arbitrary varia...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
FPL
2001
Springer
88views Hardware» more  FPL 2001»
15 years 11 months ago
FPGA-Based Discrete Wavelet Transforms System
Although FPGA technology offers the potential of designing high performance systems at low cost, its programming model is prohibitively low level. To allow a novice signal/image pr...
Mokhtar Nibouche, Ahmed Bouridane, Fionn Murtagh, ...