23406 search results - page 422 / 4682 » Architecture, Design, Implementation |
344
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GLVLSI
2011
IEEE
14 years 10 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
176
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AEI
2006
15 years 7 months ago
2006
The worldwide population of elderly people is growing rapidly and in the coming decades the proportion of older people in the developed countries will change significantly. This d...
153
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HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
162
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MICRO
1999
IEEE
15 years 11 months ago
1999
IEEE
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
223
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EUMAS
2006
15 years 8 months ago
2006
Current IT application domains such as web services and autonomic computing call for highly flexible systems, able to automatically adapt to changing operational environments as w...