23406 search results - page 416 / 4682 » Architecture, Design, Implementation |
166
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ARC
2008
Springer
15 years 8 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
161
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ERSA
2009
15 years 4 months ago
2009
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
200
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RECONFIG
2008
IEEE
16 years 1 months ago
2008
IEEE
This paper describes an efficient arithmetic processor for elliptic curve cryptography. The proposed processor consists of special architectural components, the most important of...
194
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FCCM
2005
IEEE
16 years 13 days ago
2005
IEEE
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
191
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ISSS
2002
IEEE
15 years 11 months ago
2002
IEEE
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...