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IWSSD
2000
IEEE
15 years 11 months ago
Issues in Analyzing the Behavior of Event Dispatching Systems
A good architecture is a necessary condition to guarantee that the expected levels of performance, availability, fault tolerance, and scalability are achieved by the implemented s...
Giovanni Bricconi, Emma Tracanella, Elisabetta Di ...
ISCAS
2008
IEEE
287views Hardware» more  ISCAS 2008»
16 years 1 months ago
A high speed word level finite field multiplier using reordered normal basis
— Reordered normal basis is a certain permutation of a type II optimal normal basis. In this paper, a high speed design of a word level finite field multiplier using reordered ...
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmad...
DATE
2003
IEEE
151views Hardware» more  DATE 2003»
16 years 2 days ago
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
Adrijean Andriahantenaina, Hervé Charlery, ...
DELTA
2002
IEEE
15 years 11 months ago
Smart Antenna Software Radio Test System
This paper covers the concept, architecture, development and demonstration of a Smart Antenna Software Radio Test System (SASRATS). SASRATS was designed and developed as a functio...
Peter J. Green, Desmond P. Taylor
ICWS
2007
IEEE
15 years 8 months ago
Rich Services: The Integration Piece of the SOA Puzzle
One of the key challenges to successful systems-ofsystems integration using Web services technologies is how to address crosscutting architectural concerns such as policy manageme...
Matthew Arrott, Barry Demchak, Vina Ermagan, Claud...