Sciweavers

2237 search results - page 89 / 448
» Architectural design and evaluation of an efficient Web-craw...
Sort
View
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
16 years 50 min ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane
DATE
2008
IEEE
168views Hardware» more  DATE 2008»
16 years 25 days ago
A methodology for improving software design lifecycle in embedded control systems
Control design and real-time implementation are usually performed in isolation. The effects of the computer implementation on control system performance are still evaluated on the...
Mohamed El Mongi Ben Gaid, Rémy Kocik, Yves...
DAC
2006
ACM
16 years 7 months ago
Efficient detection and exploitation of infeasible paths for software timing analysis
Accurate estimation of the worst-case execution time (WCET) of a program is important for real-time embedded software. Static WCET estimation involves program path analysis and ar...
Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, T...
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 10 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli
ERSA
2008
130views Hardware» more  ERSA 2008»
15 years 7 months ago
Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs
Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Ch...
Masaru Kato, Yohei Hasegawa, Hideharu Amano